The principle of dynamic storage relies on the holding, for a very short period of about one millisecond, of the charge of a capacitance associated with a MOS transistor. Thus, a dynamic memory is characterized especially by its period of retention of a piece of information. This sets the minimum data refreshing frequency needed to preserve the information in the memory. The refreshing of the data is obtained by setting up a read type access and then a write type access on each of the cells of the memory.
The retention time of a dynamic memory depends on the technology used, variations inherent in the manufacturing process, the structure of the memory cell, the supply and bias voltages used, and the memory. The retention time is tested on each of the cells of the dynamic memories at the end of manufacture. The testing of this retention time actually comprises two steps.
A first step known as a characterizing step includes making very precise measurements of this retention time on one or more cells of a batch of dynamic memory circuits. A value is obtained characterizing the memory and its method of manufacture for a batch or series of batches. The measurement of the retention time is done in practice by successive approximations, in specifying the real retention time by increasingly approaching values. In one practical example, a "1" is written in a cell of the dynamic memory, then reread at the end of one millisecond for example. If a "0" is read, it means that the information has been lost. Since the data has been lost, the "1" has to be rewritten and then a read access has to be done again, but at the end of a shorter period of time, such as, 500 microseconds for example. If a "1" is read, it means that the retention time in the example ranges from 500 microseconds to 1 millisecond.
Since a "1" has been read, the read access has refreshed the data element. It is possible to carry out a new read access after a slightly longer period of time, such as, 750 microseconds, for example. This procedure is continued until the value of the retention time has been specified with sufficient precision.
Once one or more manufactured batches of DRAMs have been characterized, all the memories of these lots are tested. This operation is designed to ascertain that all the cells of all these memories have a retention time included in the interval that has been measured for characterization. This is the testing step.
This testing step is very lengthy. Indeed, the retention time has to be guaranteed for each of the cells of each of the memories. Furthermore, it is not possible to limit the operations to only one reading per cell. Ideally it is necessary, in each memory, to measure these values for all the positions of a single `1` among the zeros and a single zero among the `1`'s. In practice, only 5 or 6 readings are done per cell with tests known as zero-field tests, one-field tests, and checkerboard pattern tests.
Even if it is possible to carry out word access operation, the retention times with current technologies being about 1 millisecond, it is already necessary to take up nearly 25 seconds for testing just one 1-megabit memory. The testing of the dynamic memories is therefore very lengthy which means that it is very costly.